The present invention relates generally to chip stacks, and more particularly to a chip stack including a uniquely configured flex circuit which allows different types of packaged chips to be placed into electrical communication with each other in a stacked configuration.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. However, one major drawback associated with currently known chip stack arrangements and chip stacking techniques is the inability to quickly, easily and inexpensively create chip stacks including dissimilar packaged chips, i.e., packaged chips of differing types.
The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of a uniquely configured flex circuit or substrate specifically adapted to allow multiple chip packages including different types of packaged chips to be electrically interconnected to each other in a stacked configuration or arrangement. For example, a chip stack constructed in accordance with the present invention incorporating the flex circuit thereof may include a mixture of TSOP and BGA (ball grid array) packaged chips or devices, or a mixture of discrete or passive encased devices. The flex circuit also provides various advantages in the assembly of the chip stack, including significantly greater ease in achieving and maintaining the alignment between the chip packages having the dissimilar packaged chips. These, and other advantages of the present invention, will be discussed in more detail below.